14

Barrier layer thickness analysis for reliable copper plug process in CMOS technology

Year:
2011
Language:
english
File:
PDF, 1.21 MB
english, 2011
27

Numerical investigation on the junctionless nanowire FET

Year:
2012
Language:
english
File:
PDF, 1.01 MB
english, 2012
28

Perspective of flash memory realized on vertical Si nanowires

Year:
2012
Language:
english
File:
PDF, 1.74 MB
english, 2012
44

Modeling of gate-all-around charge trapping SONOS memory cells

Year:
2010
Language:
english
File:
PDF, 1.07 MB
english, 2010